介绍了一种具有高输出功率的功率放大器,设计利用的是两路伪差分电路结构,每一条支路都由两级电路构成,第一级电路为驱动级电路,第二级电路为功率级电路。电路的匹配网络由传输线和电容构成,以保证信号能够高效率地传输。用威尔金森功分器将两支路结合在一起,通过调试功率分配器使整体电路到达最优化。功率放大器属于AB类放大器,采用0.13um Si Ge Bi CMOS工艺,在中心频率30GHz时得到整体电路后仿真结果:输出1dB压缩点OP1dB=22.91dBm,功率增益GP=25.52dB。
This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.
