In order to improve the performance of the existing phase frequency detectors （PFDs）, a systematical analysis of the existing PFDs is presented. Based on the circuit architecture, both classifications and comparisons are made. A new robust CMOS phase frequency detector for a high speed and low jitter charge pump phrase-locked loop （PLL） is designed. The proposed PFD consists of two rising-edge triggered dynamic D flip-flops, two positive-edge detectors and delaying units and two OR gates. It adopts two reset mechanisms to avoid the LIP and DN signals to be logic-1 simultaneously. Thus, any current mismatch of the charge pump circuit will not worsen the performance of the PLL. Furthermore, it has hardly any dead-zone phenomenon in phase characteristic. Simulations with ADS are performed based on a TSMC 0. 18-μm CMOS process with a 1.8-V supply voltage. According to the theoretical analyses and simulation results, the proposed PFD shows a satisfactory performance with a high operation frequency （≈ 1 GHz）, a wide phase-detection range [ ± 2π], a near zero dead-zone （ 〈 0. 1 ps）, high reliability, low phase jitter, low power consumption （ ≈100 μW） and small circuit complexity.
