To control the electron beam emitted from the carbon nanotube （CNT） cathode, four different electron chunnels are designed. A common basic structure used in the simulation is an insulating chunnel. When primary electrons hit the surface of the chunnel, secondary electrons are generated, which make the electron distribution at the exit hole of the chunnel more uniform. By analyzing and comparing the state of electrons emitted from the exit of chunnel among the four structures, an optimal structure is obtained. In the optimized structure, the electron distribution at the exit hole of the chunnel is more uniform and the electron beam is rather slim. Furthermore, by adding a magnetic field along the slow wave line, the electron beam can be constrained. In the optimized structure, a very small magnetic field is needed to make most of electrons pass through the slow wave line.
To correct the S-distortion in large deflection angle cathode-ray tubes （CRTs）,ideal deflection current waveforms are proposed to realize S-correction.Analysis was done for homogenous and non-homogenous magnetic fields, plane and curved screen.For the convenience of circuit design,high order sine waveforms are used to approach the ideal deflection current.After optimization,the deflection current is acceptably close to the ideal one,for a deflection angle range from 90° up to 140°.Harmonic current rank rises to four as the deflection angle reaches 140°.A ladder-type driving circuit to realize these sine wave series is also presented.Simulation and experiments prove the proposed method can correct the S-distortion in a very slim CRT.
The power consumption and electric field distribution in a field emission display （FED） panel is optimized with a novel pixel structure. A circuit model is proposed to estimate the total power consumption in an FED panel which is composed of anode energy consumption, energy loss due to the leakage current and the energy dissipated in the parasitic capacitances. Moreover, the parasitic capacitances play a vital part in the power consumption and driving performance. In order to lower the parasitic capacitances, multiple dielectric layers are used as the gate electrode. Due to different etching speeds, a novel pixel structure is formed. As a result, the power consumption of an FED panel is reduced by 28% in a full white picture, and the electron beam performance is also better than that of the conventional structure.
