The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.Based on the proposed models,an optimal stack generation technique is developed to control the parasitics and mismatches,optimize the stack shape and ensure the generation of an Eulerian graph for a given CMOS analog module.An OPA circuit example is given to demonstrate that the circuit performances such as unit gain bandwidth and phase margin are enhanced by the proposed layout optimization method.
