With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub\|micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi\|wafers can meet such high requirements. The current development of researches on the 150mm silicon epi\|wafers for advanced IC applications is described. The P/P\++ CMOS silicon epi\|wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epi\|wafers, such as epi\|defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi\|layer were characterized in detail. It is demonstrated that the 150mm silicon epi\|wafers on PE2061 can meet the stringent requirements for the advanced IC applications.
