Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit （3D IC） is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip （SOC） is established by evaluating the constraints of 1） wiring resource, 2） wiring bandwidth, and 3） wiring noise. In comparison to a two-dimensional integrated circuit （2D IC） in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.
