A novel low specific on-resistance （Ron,sp） silicon-on-insulator （SO1） p-channel lateral double-diffused metal-oxide semiconductor （pLDMOS） compatible with high voltage （HV） n-channel LDMOS （nLDMOS） is proposed. The pLDMOS is built in the N-type SO1 layer with a buried P-type layer acting as a current conduction path in the on-state （BP SOl pLD- MOS）. Its superior compatibility with the HV nLDMOS and low voltage （LV） complementary metal-oxide semiconductor （CMOS） circuitry which are formed on the N-SOl layer can be obtained. In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping, leading to an enhanced （reduced） surface field （RESURF） effect. The proposed BP SO1 pLDMOS achieves not only an improved breakdown voltage （BV） but also a significantly reduced Ron,sp. The BV of the BP SO1 pLDMOS increases to 319 V from 215 V of the conventional SO1 pLDMOS at the same half cell pitch of 25 μm, and Ron,sp decreases from 157 mΩ.cm2 to 55 mΩ.cm2. Compared with the PW SO1 pLDMOS, the BP SO1 pLDMOS also reduces the Ron,sp by 34% with almost the same BV.
A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.
本文提出一种高k介质电导增强SOI LDMOS新结构(HK CE SOI LDMOS),并研究其机理.HK CE SOI LDMOS的特征是在漂移区两侧引入高k介质,反向阻断时,高k介质对漂移区进行自适应辅助耗尽,实现漂移区三维RESURF效应并调制电场,因而提高器件耐压和漂移区浓度并降低导通电阻.借助三维仿真研究耐压、比导通电阻与器件结构参数之间的关系.结果表明,HK CE SOI LDMOS与常规超结SOI LDMOS相比,耐压提高16%—18%,同时比导通电阻降低13%—20%,且缓解了由衬底辅助耗尽效应带来的电荷非平衡问题.
A new silicon-on-insulator （SOI） power lateral MOSFET with a dual vertical field plate （VFP） in the oxide trench is proposed. The dual VFP modulates the distribution of the electric field in the drift region, which enhances the internal field of the drift region and increases the drift doping concentration of the drift region, resulting in remarkable improvements in breakdown voltage （BV） and specific on-resistance （Ron,sp）. The mechanism of the VFP is analyzed and the characteristics of BV and Ron,sp are discussed. It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V, and the Ron,sp decreases from 366 mΩ·cm2 to 110 mΩ·cm2.
A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.
A low specific on-resistance（Ron,sp） integrable silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer（BOX）（DGRD MOSFET）.First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage（BV）.The BV of 233 V and Ron,sp of 4.151 mΩ·cm2（VGS = 15 V） are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.
An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.
An integrable silicon-on-insulator （SOl） power lateral MOSFET with a trench gate and a recessed drain （TGRD MOSFET） is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide （BOX） and the recessed drain reduce the specific on-resistance （Ron, sp） by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage （BV） of 97 V and Ron, sp of 0.985 mf2-cm2 （l/os = 5 V） are obtained for a TGRD MOSFET with 6.5/xm half-cell pitch. Compared with the trench gate SOI MOSFET （TG MOSFET） and the conventional MOSFET, Ron＇ sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain （TGTD MOSFET）, BV of the TGRD MOSFET increases by 37% at the same Ron,sp.
A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.
An analytical model for a novel high voltage silicon-on-insulator device with composite-k （relative per mittivity） dielectric buried layer （CK SOl） is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k （k = 2.65） dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage （BV） is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional （2-D） potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 （LK SOl）, simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.
