In the course of high-level synthesis of integrate circuit, the hard-to-test structure caused by irrational schedule and allocation reduces the testability of circuit. In order to improve the circuit testability, this paper proposes a weighted compatibility graph (WCG), which provides a weighted formula of compatibility graph based on register allocation for testability and uses improved weighted compatibility clique partition algorithm to deal with this WCG. As a result, four rules for testability are considered simultaneously in the course of register allocation so that the objective of improving the design of testability is acquired. Tested by many experimental results of benchmarks and compared with many other models, the register allocation algorithm proposed in this paper has greatly improved the circuit testability with little overhead on the final circuit area.
Network on chip (NoC) architectures have been proposed to resolve complex on-chip communication problems. An NoC-based mapping algorithm is shown in this paper. It can map irregular intellectual properties (IPs) cores onto regular tile 2-D mesh NoC architectures. The basic idea is to decompose a large IP into several dummy IPs or integrate several small IPs into one dummy IP, such that each dummy IP can fit into a single tile. It can also allocate buffer space according to the input/output degree and avoid connection congestion by adapting communication density. Experimental data indicate that using the algorithm proposed in this paper, the communication energy can be reduced about 7%.
采用多项式符号代数理论建立了包含时序元件的整个同步时序电路的统一多项式符号描述形式,并采用WGL(weighted general lists)模型进行多项式的符号运算.在时序电路统一多项式描述和及其WGL运算的基础上,通过对有限状态机的简化比较,提出一种完全考虑周期的时序特性的时钟周期确定算法.该方法打破了传统上认为时钟周期要不小于实际传输延迟的认识;通过对多种现有方法的实验比较,该方法可以在不增加计算复杂度的情况下比现有方法找到更精确的时钟周期;实验还表明电路正常工作的时钟周期可以在不使用流水的情况下比实际传输延迟小很多.
