We present both a theoretical and experimental demonstration of a fully differential variable gain am- plifier （VGA） with small total harmonic distortion （THD） for an electrocardiogram （ECG） acquisition system. Capacitive feedback technology is adopted to reduce the nonlinearity of VGA. The fully differential VGA has been fabricated in SMIC 0.18-μm CMOS process, and it only occupies 0.11 mm2. The measurements are in good agreement with simulation results. Experimental results show that the gain of VGA changes from 6.17 to 43.75 dB with a gain step of 3 dB. The high-pass comer frequency and low-pass comer frequency are around 0.22 Hz and 7.9 kHz, respectively. For each gain configuration, a maximal THD of 0.13% is obtained. The fully differential VGA has a low THD and its key performance parameters are well satisfied with the demands of ECG acquisition system application in the UWB wireless body area network.
A fifth order operational transconductance amplifier-C （OTA-C） Butterworth type low-pass filter with highly linear range and less passband attenuation is presented for wearable bio-telemetry monitoring applications in a UWB wireless body area network. The source degeneration structure applied in typical small transconduc- tance circuit is improved to provide a highly linear range for the OTA-C filter. Moreover, to reduce the passband attenuation of the filter, a cascode structure is employed as the output stage of the OTA. The OTA-based circuit is operated in weak inversion due to strict power limitation in the biomedical chip. The filter is fabricated in a SMIC 0.18-μm CMOS process. The measured results for the filter have shown a passband gain of -6.2 dB, while the -3-dB frequency is around 276 Hz. For the 0.8 Vpp sinusoidal input at 100 Hz, a total harmonic distortion （THD） of-56.8 dB is obtained. An electrocardiogram signal with noise interference is fed into this chip to validate the function of the designed filter.
This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.
An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio （PSRR） and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/℃ in a range from 25 to 100 ℃. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3,3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs.
A CMOS active mixer based on voltage control load technique which can operate at 1.0 V supply voltage was proposed, and its operation principle, noise and linearity analysis were also presented. Contrary to the conventional Gilbert-type mixer which is based on RF current-commutating, the load impedance in this proposed mixer is controlled by the LO signal, and it has only two stacked transistors at each branch which is suitable for low voltage applications. The mixer was designed and fabricated in 0.18 tam CMOS process for 2.4 GHz ISM band applications. With an input of 2.44 GHz RF signal and 2.442 GHz LO signal, the measurement specifications of the proposed mixer are： the conversion gain （Gc） is 5.3 dB, the input-referred third-order intercept point （PIIP3） is 4.6 dBm, the input-referred 1 dB compression point （P1dB） is --7.4 dBm, and the single-sideband noise figure （NFSSB） is 21.7 dB.
