Sb rich Ge_(2)Sb_(5)Te_(5) materials are investigated for use as the storage medium for high-speed phase change memory(PCM).Compared with conventional Ge2Sb2Te5,Ge_(2)Sb_(5)Te_(5) films have a higher crystallisation temperature(~200℃),larger crystallisation activation energy(3.13 eV),and a better data retention ability(100.2℃ for ten years).A reversible switching between set and reset states can be realised by an electric pulse as short as 5 ns for Ge_(2)Sb_(5)Te_(5)-based PCM cells,over 10 times faster than the Ge_(2)Sb_(5)Te_(5)-based one.In addition,Ge2Sb2Te5 shows a good endurance up to 3×10^(6) cycles with a resistance ratio of about three orders of magnitude.This work clearly reveals the highly promising potential of Ge_(2)Sb_(5)Te_(5) films for applications in high-speed PCM.
The endurance characteristics of phase change memory are studied. With operational cycles, the resis- tances of reset and set states gradually change to the opposite direction. What is more, the operational conditions that are needed are also discussed. The thilure and the changes are concerned with the compositional change of the phase change material. An abnormal phenomenon that the threshold voltage decreases slightly at first and then increases is observed, which is due to the coaction of interthce contact and growing active volume size changing.
A low ripple switched capacitor charge pump applicable to phase change memory （PCM） is presented. For high power efficiency, the selected charge pump topology can automatically change the power conversion ratio between 2X/1.5X modes with the input voltage. For a low output ripple, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo- 14n during the charge phase （Vo is the prospective output voltage）. In the discharge phase, the flying capacitor is placed in series with the Vin to transfer energy to the output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 1.6-2.1 V in on SMIC standard 40 nm CMOS process, the result shows that the new operation mode could regulate the output of about 2.5 V with a load condition from 0 to 10 mA, and the ripple voltage is lower than 4 mV. The maximum power efficiency reaches 91%.
Phase change random access memory （PCRAM） is one of the best candidates for next generation non- volatile memory, and phase change SiESbETe5 material is expected to be a promising material for PCRAM. In the fabrication of phase change random access memories, the etching process is a critical step. In this paper, the etching characteristics of Si2Sb2Te5 films were studied with a CF4/Ar gas mixture using a reactive ion etching system. We observed a monotonic decrease in etch rate with decreasing CF4 concentration, meanwhile, Ar concentration went up and smoother etched surfaces were obtained. It proves that CF4 determines the etch rate while Ar plays an im- portant role in defining the smoothness of the etched surface and sidewall edge acuity. Compared with GeESbETe5, it is found that Si2Sb2Te5 has a greater etch rate. Etching characteristics of Si2SbETe5 as a function of power and pressure were also studied. The smoothest surfaces and most vertical sidewalls were achieved using a CF4/Ar gas mixture ratio of 10/40, a background pressure of 40 mTorr, and power of 200 W.
The dry etching characteristic of AlSbTe film was investigated by using a CF/Ar gas mixture.The experimental control parameters were gas flow rate into the chamber,CF/Ar ratio,the Oaddition,the chamber background pressure,and the incident RF power applied to the lower electrode.The total flow rate was 50 sccm and the behavior of etch rate of AlSbTe thin films was investigated as a function of the CF/Ar ratio,the Oaddition,the chamber background pressure,and the incident RF power.Then the parameters were optimized.The fast etch rate was up to 70.8 nm/min and a smooth surface was achieved using optimized etching parameters of CFconcentration of 4%,power of 300 W and pressure of 80 mTorr.
A fully integrated low-jitter, precise frequency CMOS phase-locked loop （PLL） clock for the phase change memory （PCM） drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector （PFD） with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator （VCO）, a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 #m CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM＇s program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.
A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.
Phase change memory （PCM） has been regarded as a promising candidate for the next generation of nonvolatile memory. To decrease the power required to reset the PCM cell, titanium nitride （TIN） is preferred to be used as the bottom electrode of PCM due to its low thermal and suitable electrical conductivity. However, during the manufacture of PCM cell in 40 nm process node, abnormally high and discrete distribution of the resistance of TiN bottom electrode was found, which might be induced by the surface oxidation of TiN bottom electrode during the photoresist ashing process by oxygen plasma. In this work, we have studied the oxidation of TiN and found that with the increasing oxygen plasma ashing time, the thickness of the TiO2 layer became thicker and the state of the TiO2 layer changed from amorphous to crystalline, respectively. The resistance of TiN electrode contact chain with 4-5 nm TiO2 layer was confirmed to be almost three-orders of magnitude higher than that of pure TiN electrode, which led to the failure issue of PCM cell. We efficiently removed the oxidation TiO2 layer by a chemical mechanical polishing （CMP） process, and we eventually recovered the resistance of TiN bottom electrode from 1×10^5Ω/via back to 6×10^2 Ωvia and successfully achieved a uniform resistance distribution of the TiN bottom electrode.
Strained Si is recognized as a necessary technology booster for modem integrated circuit technology. However, the thermal oxidation behaviors of strained Si substrates are not well understood yet despite their importance. In this study, we for the first time experimentally find that all types of strained Si substrates （uniaxial tensile, uniaxial compressive, biaxial tensile, and biaxial compressive） show smaller thermal oxidation rates than an unstrained Si substrate. The possible mechanisms for these retarded thermal oxidation rates in strained Si substrates are also discussed.
