Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .
Phase noise analysis of an oscillator is implemented with its periodic time-varying small signal state equations by perturbing the autonomous large signal state equations of the oscillator. In this paper, the time domain steady solutions of oscillators are perturbed with traditional regular method; the periodic time-varying Jocobian modulus matrices are decomposed with Sylvester theorem, and on the resulting space spanned by periodic vectors, the conditions under which the oscillator holds periodic steady states with any perturbations are analyzed. In this paper, stochastic calculus is applied to disclose the generation process of phase noise and calculate the phase jitter of the oscillator by injecting a pseudo sinusoidal signal in frequency domain, representing the white noise, and a δcorrelation signal in time domain into the oscillator. Applying the principle of frequency modulation, we learned how the power-law and the Lorentzian spectrums are formed. Their relations and the Lorentzian spectrums of harmonics are also worked out. Based on the periodic Jacobian modulus matrix, the simple algorithms for Floquet exponents and phase noise are constructed, as well as a simple case is demonstrated. The analysis difficulties and the future directions for the phase noise of oscillators are also pointed out at the end.
FAN JianXingYANG HuaZhongWANG HuiYAN XiaoLangHOU ChaoHuan
A modified reduced-order method for RC networks which takes a division-and-conquest strategy is presented.The whole network is partitioned into a set of sub-networks at first,then each of them is reduced by Krylov subspace techniques,and finally all the reduced sub-networks are incorporated together.With some accuracy,this method can reduce the number of both nodes and components of the circuit comparing to the traditional methods which usually only offer a reduced net with less nodes.This can markedly accelerate the sparse-matrix-based simulators whose performance is dominated by the entity of the matrix or the number of components of the circuits.
A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulation shows that this method can boost the input-referred 3rd-order intercept point with much less power dissipation than that of traditional power/linearity tradeoff solution which pays at least 1dB power for 1dB linearity improvement.It is also shown that the size of the common-gate PMOS transistor needs to be optimized to reduce its loaded input impedance so as not to degrade the linearity due to high voltage gain at its source terminal.The simulation is carried out with TSMC 0.18μm RF CMOS technology and SpectreRF.
This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.
