设计了一款应用于有源相控阵雷达T/R组件的X波段功率放大器,放大器采用单端两级放大的共源共栅结构,包括输入与输出匹配网络,偏置电路采用自适应线性化技术,实现高增益和高线性的输出。基于IBM 0.18μm Si Ge Bi CMOS 7WL工艺流片,测试结果表明,在3.3 V电源电压下,在8.5 GHz时增益为21.8 d B,1 d B压缩点输出功率为10.4 d Bm,输入输出匹配良好,芯片面积为1.4 mm×0.8 mm。芯片面积较小,实现了与整个T/R芯片的集成。
A fully integrated 60-GHz transceiver for 802.11ad applications with superior performance in a 90-nm CMOS process versus prior arts is proposed and real based on a field-circuit co-design methodology.The reported transceiver monolithically integrates a receiver,transmitter,PLL(Phase-Locked Loop)synthesizer,and LO(Local Oscillator)path based on a sliding-IF architecture.The transceiver supports up to a 16QAM modulation scheme and a data rate of 6 Gbit/s per channel,with an EVM(Error Vector Magnitude)of lower than−20 dB.The receiver path achieves a configurable conversion gain of 36~64 dB and a noise figure of 7.1 dB over 57~64 GHz,while consuming only 177 mW of power.The transmitter achieves a conversion gain of roughly 26 dB,with an output P1dB of 8 dBm and a saturated output power of over 10 dBm,consuming 252 mW of power from a 1.2-V supply.The LO path is composed of a 24-GHz PLL,doubler,and a divider chain,as well as an LO distribution network.In closed-loop operation mode,the PLL exhibits an integrated phase error of 3.3ºrms(from 100 kHz to 100 MHz)over prescribed frequency bands,and a total power dissipation of only 26 mW.All measured results are rigorously loyal to the simulation.
This paper presents a millimeter wave （mm-wave） oscillator that generates signal at 36.56 GHz. The ram-wave oscillator is realized in a UMC 0.18 μm CMOS process. The linear superposition （LS） technique breaks through the limit of cut-off frequency （JET）, and realizes a much higher oscillation than Jr. Measurement results show that the LS oscillator produces a calibrated 37.17 dBm output power when biased at 1.8 V; the output power of fundamental signal is -10.85 dBm after calibration. The measured phase noise at 1 MHz frequency offset is -112.54 dBc/Hz at the frequency of 9.14 GHz. This circuit can be properly applied to mm-wave communication systems with advantages of low cost and high integration density.
An asymmetric Doherty architecture based on three identical transistors is proposed in this paper. This proposed three.way topology reduces the difficulty in designing matching networks brought by the low optimal impedance of high power transistors. And the inverted Doherty topology as well as carefully chosen value of load impedance makes it possible to extend the bandwidth of high power amplifiers. Besides, bias networks of this proposed three.way architecture are also carefully considered to improve the linearity. The proposed high power three.way Doherty power amplifier(3W.DPA) is designed and fabricated based on theoretic analysis. Its maximum output power is about 600 Watts and the drain efficiency is above 35.5% at 9d B back off output power level from 1.9GHz to 2.2 GHz and the saturated drain efficiency is above 47% across the whole frequency band. The measured concurrent two.tone results suggest that the linearity of DPA is improved by at least 5d B.
