A novel buck/LDO dual-mode （BLDM） converter using a multiplexing power MOS transistor is proposed, which adaptively switches between buck mode and LDO mode to improve conversion efficiency. The chip was fabricated in a standard 0.35 #m CMOS process. Measurement results show that the peak efficiency is 97%. For the light load operation, the efficiency is improved by 14%. The efficiency keeps higher than 82.5% for the load current of 50 mA without any complex control or extra EMI due to the normal method of pulse frequency modulation （PFM） control used for improving the light load efficiency. It does not cost much extra chip area because no additional regulator PMOS is needed. It is more suitable for noise-restricted systems and battery-powered electronic devices for when battery voltage drops because of long hours of work.
动态电压频率调整(Dynamic Voltage Frequency Scaling,DVFS)可以使系统在高电压工作时获得高性能,在低电压工作时降低系统功耗,它要求电路能够从正常电压一直到亚阈值区范围内均能正常工作.抗辐照DVFSSRAM的设计面临着低压工作稳定性及工艺、电压、温度偏差(Process,Voltage,Temperature,PVT)的严重影响.本文针对以上问题,设计了一款适应于DVFS应用的抗辐照静态随机存储器(Static Random Access Memory,SRAM).提出了新型抗辐照DICE单元结构,其读噪声容限相对于原有DICE单元有大幅提升.同时,针对常规分级位线结构时序控制电路存在的问题,提出了改进型复制列技术,增强了SRAM存储体在不同PVT环境下工作的稳定性.对SRAM存储体进行了电路设计及版图设计,后仿真结果表明,设计的512bit SRAM存储体可在0.6V^1.8V电源电压下正常工作.在1.8V下,SRAM的存取速度为5.1ns,功耗为1.8mW;在0.6V电压下,SRAM的存取速度为93.5ns,功耗为14.63μW,比1.8 V电源工作时的功耗降低了约100倍.另外,设计的SRAM对宽度为300ps以下的单粒子瞬态脉冲具有滤除能力,对单粒子翻转效应有良好的抵抗能力.
基于45nm SOI CMOS工艺,设计了一款两级流水线级联型逐次逼近ADC(Pipeline-SAR ADC).摒弃了传统流水线结构中大功耗级间运算放大器,采用过零比较器和受控电流源完成级间余量放大功能,极大地减小了ADC的功耗.分析了子ADC中比较器失调对ADC精度的影响,提出了一种具有失调校准的动态比较器,满足了高精度、高速度的要求.此外,在设计逐次逼近结构时,采用共模切换、上极板采样和全定制控制逻辑等技术进一步降低了系统功耗.仿真结果显示,ADC在125 MS/s、奈圭斯特输入频率下,实现了60.46dB的信噪失真比和77.33dB的无杂散动态范围,有效位数为9.75bit,系统总功耗只有1mW.ADC的FoM值仅为9.29fJ/step,较其他工作有很大的提升.
